1. Field of the Invention
The present invention relates to a field effect transistor (FET) including a semiconductor.
2. Description of the Related Art
In a field effect transistor (hereinafter referred to as a FET), regions called a source and a drain are provided in a semiconductor. Voltage is applied to the semiconductor from a region called a gate through an insulating film or a Schottky barrier in the state where voltage is applied between the source and the drain, so that the state of the semiconductor is controlled; thus, current flowing between the source and the drain is controlled. As the semiconductor, an element such as silicon or germanium, a compound such as gallium arsenide, indium phosphide, gallium nitride, zinc sulfide, or cadmium telluride, or the like can be used.
In recent years, FETs including an oxide such as zinc oxide or an indium gallium zinc oxide-based compound as the semiconductor have been reported (Patent Document 1 and Patent Document 2). In a FET including such an oxide semiconductor, relatively high mobility can be obtained, and such a material has a wide band gap of greater than or equal to 3 electron volts; therefore, application of the FET including an oxide semiconductor to displays, power devices, and the like is discussed.
Meanwhile, so far there have been few reports on an oxide semiconductor which contains zinc or indium and has p-type conductivity. Thus, an oxide semiconductor using a PN junction like a silicon FET has not been reported. As in Patent Document 1 and Patent Document 2, a source and a drain are formed using a metal-semiconductor junction in which an n-type or i-type oxide semiconductor (in this specification, a semiconductor whose concentration of carriers derived form a donor is 1012/cm3 or lower is called an i-type semiconductor) is in contact with metal electrodes.
Note that in a FET having a sufficiently long channel, donor concentration is substantially equal to carrier concentration. However, in a FET having a short channel (for example, the channel length is 0.2 μm or smaller), the donor concentration is not always equal to the carrier concentration (or electron concentration). In this specification, the FET having a sufficiently long channel length will be discussed below.
Unlike a PN-junction FET, in a FET where a source and a drain are formed using a metal-semiconductor junction, when the carrier concentration in a semiconductor is high, current (off-state current) flows between the source and the drain even in an off state. Therefore, the off-state current has needed to be reduced by lowering the carrier concentration in the semiconductor so that an i-type semiconductor is obtained.
FIGS. 4A to 4C are cross-sectional views illustrating an example of processes for manufacturing a conventional bottom-gate FET including an oxide semiconductor. FIGS. 4A to 4C are cross sections along line A-B in FIG. 4D. First, a conductive layer is formed over a substrate 201 and etched into a desired shape, so that wirings 202a and 202b which also function as gate electrodes are formed. The wirings 202a and 202b are also used as wirings in circuits (for example, scan lines in an active-matrix display device).
Then, an insulating film 203 which also functions as a gate insulating film is formed so as to cover the wirings 202a and 202b. Further, an oxide semiconductor layer is formed and etched into a desired shape, so that semiconductor layers 204a and 204b are obtained (FIG. 4A). A top view of this stage is FIG. 4D.
Next, another conductive layer which is in contact with the semiconductor layers 204a and 204b is formed and etched into a desired shape, so that wirings 205a and 205b are obtained (FIG. 4B). Part of the wirings 205a and 205b also function as a source and a drain of the semiconductor layers 204a and 204b. 
The wirings 205a and 205b can be directly used as wirings in circuits (for example, data lines in an active-matrix display device); however, in that case, parasitic capacitance between the wirings is high because only the insulating film 203 is placed between the wirings 202a and 202b and the wirings 205a and 205b. 
In particular, in a FET using a metal-semiconductor junction, when a gate insulating film is thicker, the threshold voltage shifts negatively (in the case of an n-channel FET) and the FET is normally on. Therefore, the thickness of the insulating film 203 needs to be 100 nm or less; however, in that case, the parasitic capacitance between the wirings 202a and 202b and the wirings 205a and 205b becomes higher.
Because of such problems, a planarization insulating layer 206 is usually formed as illustrated in FIG. 4C. Openings reaching the wirings 205a and 205b are formed in the planarization insulating layer 206, and wirings 207a and 207b are further formed so as to be connected to the wirings 205a and 205b through the openings. The wirings 207a and 207b are used as data lines in an active-matrix display device for example.
Meanwhile, it has been pointed out that hydrogen is a source for supplying carriers particularly in an oxide semiconductor. Therefore, some measures need to be taken to prevent hydrogen from entering the oxide semiconductor at the time of depositing the oxide semiconductor. It is also pointed out that hydrogen needs to be prevented from entering not only the oxide semiconductor but also an insulating film in contact with the oxide semiconductor (see Patent Document 3).
In order to prevent the entrance of hydrogen, it is considered that the insulating film 203 is preferably formed by a sputtering method in which a material that hardly contains hydrogen can be used instead of a CVD method (e.g., a plasma CVD method or a low-pressure CVD method) in which a material containing hydrogen has to be used.
An insulating film formed by a sputtering method, however, does not have sufficient step coverage, resulting in an insufficient insulating property particularly in a step portion. Therefore, there is a problem in that leakage current is increased when a wiring or a semiconductor layer is formed so as to overlap with a step portion.